Recent advancements in technologies such as artificial intelligence (AI), autonomous vehicles, and cloud computing services have led to a rapid increase in the amount of generated data. It is expected that this data flood will drive up the demand for high-density, high-performance NAND Flash memory. To meet these demands, NAND Flash memory is increasing its stacked WL layers and developing additional core technologies to ensure high reliability and performance of 4-bit or higher multi-bit techniques. This advancement aims to achieve cost reduction through increased bit density. However, multi-bit technology, which involves writing and reading data to the cell devices more than the current 3-bit TLC, have issues related to the performance (tPROG, tR) and degradation of reliability (disturbance, endurance, retention). In order to develop high-density, high-performance 3D NAND Flash, it is essential to conduct research addressing these issues.

Recently, with the rapid advances of artificial intelligence, there has been an explosive surge in demand for high-density, high-performance DRAM used in graphic processing units (GPUs), high-bandwidth memory (HBM), and AI accelerators. As a result, transistors used in DRAM cells, core circuits, and peripheral circuits have evolved through scaling and structural engineering to meet these demands. However, the continuous 2D planar scaling has reached its physical limits since patterning difficulty. Introducing expensive extreme ultraviolet lithography (EUV) aimed to address this issue, but the complexity of patterning and increased manufacturing cost has made it challenging to reduce the cost per bit. Moreover, the ongoing planar scaling has compromised the mechanical stability of the structure, leading to interference among various modules and resulting in multiple failures. Therefore, it is essential to transition from the existing 6F² structure to a 4F² structure with vertical channel transistors or 3D DRAM structure similar to the 3D NAND, in order to overcome these issues and enable continuous improvement in DRAM integration density.